To fabricate microelectronic semiconductor devices such as an integrated circuit (IC), many different layers of metal and insulation are selectively deposited on a semiconductor. The insulation layers may be, for example, silicon dioxide, silicon oxynitride, fluorinated silicate glass (FSG) and the like. These insulation layers are deposited between the metal layers, i.e., interlevel dielectric (ILD) layers, and may act as electrical insulation therebetween or serve other known functions.
The metal layers of such semiconductor devices are interconnected by metallization through vias etched in the intervening insulation layers. Additionally, interconnects are provided separately within the dielectric (e.g., insulation) layers. To accomplish this, the stacked layers of metal and insulation undergo photolithographic processing to provide a pattern consistent with a predetermined IC design. By way of example, the top layer of the structure may be covered with a photoresist layer of photo-reactive polymeric material for patterning via a mask. A photolithographic process using either visible or ultraviolet light is then directed through the mask onto the photoresist layer to expose it in the mask pattern. An antireflective coating (ARC) layer may be provided at the top portion of the wafer substrate to minimize reflection of light back to the photo resist layer for more uniform processing. The etching may be performed by anisotropic or isotropic etching as well as wet or dry etching, depending on the physical and chemical characteristics of the materials. Regardless of the fabrication process, to maximize the integration of the device components in very large scale integration (VLSI), it is necessary to increase the density of the components.
Although silicon dioxide has been used as an insulating material due to its thermal stability and mechanical strength, in recent years it has been found that improved device performance may be achieved by using a lower dielectric constant dielectric material. By using a lower dielectric constant insulator material, a reduction in the capacitance of the structure can be achieved which, in turn, increases the device speed. However, use of organic low-k dielectric materials such as, for example, SiLK® (manufactured by Dow Chemical Co., Midland, Mich.) tend to have lower mechanical strength than conventional dielectric materials such as, for example, silicon oxide.
By building a device having a low-k dielectric that is less than silicon dioxide, the large intra-level line-to-line component of wiring capacitive coupling is reduced, thus maximizing the positive benefit of the low-k material while improving the overall robustness and reliability of the finished structure. Even with prior art low dielectric constant materials including, for example, a hybrid oxide/low-k dielectric stack structure, there is still the possibility to improve even further the electrical properties of the device by lowering the effective k (keff) of a multilevel structure or a k of the dielectric material by forming voided channels within the dielectric material between the interconnects and vias. The channels are vacuum filled and have a dielectric constant of about 1. By using such channels, a higher dielectric constant dielectric material, itself, may be used to increase the overall strength of the structure without reducing the electric properties.
In known systems, sub-resolution (below 50 nm) lithographic processes have been used to create such channels. This typically consists of new manufacturing processes and tool sets which add to the overall cost of the fabrication of the semiconductor device. Also, in sub-resolution lithographic processes, it is necessary to etch wide troughs in empty spaces which, in turn, cannot be pinched off by ILD PECVD deposition. Additionally, although the channels create low line-line capacitance, there remains a high level-level capacitance for wide lines. This, of course, affects the overall electrical properties of the device. Also, air gaps can occur near the vias from a higher level, which create the risk of plating bath or metal fill at these areas. Lastly, in known processes, there is also the requirement of providing an isotropic etch which may etch underneath the interconnect thus leaving it unsupported or floating and, thus degrading the entire structural and electrical performance of the device.